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<a href="#define-members">Macros</a>  </div>
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<div class="title">xwdtps_hw.h File Reference</div>  </div>
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Macros</h2></td></tr>
<tr class="memitem:gae41b46b220ba0da6a9f28e594c3c0a47"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdtps__v3__0.html#gae41b46b220ba0da6a9f28e594c3c0a47">XWdtPs_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;Xil_In32((BaseAddress) + (u32)(RegOffset))</td></tr>
<tr class="memdesc:gae41b46b220ba0da6a9f28e594c3c0a47"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read the given register.  <a href="group__wdtps__v3__0.html#gae41b46b220ba0da6a9f28e594c3c0a47">More...</a><br /></td></tr>
<tr class="separator:gae41b46b220ba0da6a9f28e594c3c0a47"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac1cc7282f826a550a7f5107f1e12523b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdtps__v3__0.html#gac1cc7282f826a550a7f5107f1e12523b">XWdtPs_WriteReg</a>(BaseAddress,  RegOffset,  Data)&#160;&#160;&#160;Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))</td></tr>
<tr class="memdesc:gac1cc7282f826a550a7f5107f1e12523b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write the given register.  <a href="group__wdtps__v3__0.html#gac1cc7282f826a550a7f5107f1e12523b">More...</a><br /></td></tr>
<tr class="separator:gac1cc7282f826a550a7f5107f1e12523b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Register Map</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Offsets of registers from the start of the device </p>
</div></td></tr>
<tr class="memitem:gabfb6c271ee50fc3735fde379c938be0c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdtps__v3__0.html#gabfb6c271ee50fc3735fde379c938be0c">XWDTPS_ZMR_OFFSET</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memdesc:gabfb6c271ee50fc3735fde379c938be0c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Zero Mode Register.  <a href="group__wdtps__v3__0.html#gabfb6c271ee50fc3735fde379c938be0c">More...</a><br /></td></tr>
<tr class="separator:gabfb6c271ee50fc3735fde379c938be0c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga55c7e50c407f1bb66181c306fc51e3b3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdtps__v3__0.html#ga55c7e50c407f1bb66181c306fc51e3b3">XWDTPS_CCR_OFFSET</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:ga55c7e50c407f1bb66181c306fc51e3b3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Counter Control Register.  <a href="group__wdtps__v3__0.html#ga55c7e50c407f1bb66181c306fc51e3b3">More...</a><br /></td></tr>
<tr class="separator:ga55c7e50c407f1bb66181c306fc51e3b3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa8bb5ca85ad74f2e5601444673e6ed09"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdtps__v3__0.html#gaa8bb5ca85ad74f2e5601444673e6ed09">XWDTPS_RESTART_OFFSET</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:gaa8bb5ca85ad74f2e5601444673e6ed09"><td class="mdescLeft">&#160;</td><td class="mdescRight">Restart Register.  <a href="group__wdtps__v3__0.html#gaa8bb5ca85ad74f2e5601444673e6ed09">More...</a><br /></td></tr>
<tr class="separator:gaa8bb5ca85ad74f2e5601444673e6ed09"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf91a6934748dedcd7f21665696277922"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdtps__v3__0.html#gaf91a6934748dedcd7f21665696277922">XWDTPS_SR_OFFSET</a>&#160;&#160;&#160;0x0000000CU</td></tr>
<tr class="memdesc:gaf91a6934748dedcd7f21665696277922"><td class="mdescLeft">&#160;</td><td class="mdescRight">Status Register.  <a href="group__wdtps__v3__0.html#gaf91a6934748dedcd7f21665696277922">More...</a><br /></td></tr>
<tr class="separator:gaf91a6934748dedcd7f21665696277922"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Zero Mode Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register controls how the time out is indicated and also contains the access code (0xABC) to allow writes to the register </p>
</div></td></tr>
<tr class="memitem:gab5a46221cc01e7b376f46ee60f726dad"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdtps__v3__0.html#gab5a46221cc01e7b376f46ee60f726dad">XWDTPS_ZMR_WDEN_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:gab5a46221cc01e7b376f46ee60f726dad"><td class="mdescLeft">&#160;</td><td class="mdescRight">enable the WDT  <a href="group__wdtps__v3__0.html#gab5a46221cc01e7b376f46ee60f726dad">More...</a><br /></td></tr>
<tr class="separator:gab5a46221cc01e7b376f46ee60f726dad"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gace442e2a904cbae1a530f29f96e183ec"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdtps__v3__0.html#gace442e2a904cbae1a530f29f96e183ec">XWDTPS_ZMR_RSTEN_MASK</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:gace442e2a904cbae1a530f29f96e183ec"><td class="mdescLeft">&#160;</td><td class="mdescRight">enable the reset output  <a href="group__wdtps__v3__0.html#gace442e2a904cbae1a530f29f96e183ec">More...</a><br /></td></tr>
<tr class="separator:gace442e2a904cbae1a530f29f96e183ec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8ab972f80540aaa4dcab5fa69c355354"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdtps__v3__0.html#ga8ab972f80540aaa4dcab5fa69c355354">XWDTPS_ZMR_IRQEN_MASK</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:ga8ab972f80540aaa4dcab5fa69c355354"><td class="mdescLeft">&#160;</td><td class="mdescRight">enable the IRQ output  <a href="group__wdtps__v3__0.html#ga8ab972f80540aaa4dcab5fa69c355354">More...</a><br /></td></tr>
<tr class="separator:ga8ab972f80540aaa4dcab5fa69c355354"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaecc5f08ee18069fdd264027e7da22165"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdtps__v3__0.html#gaecc5f08ee18069fdd264027e7da22165">XWDTPS_ZMR_RSTLN_MASK</a>&#160;&#160;&#160;0x00000070U</td></tr>
<tr class="memdesc:gaecc5f08ee18069fdd264027e7da22165"><td class="mdescLeft">&#160;</td><td class="mdescRight">set length of reset pulse  <a href="group__wdtps__v3__0.html#gaecc5f08ee18069fdd264027e7da22165">More...</a><br /></td></tr>
<tr class="separator:gaecc5f08ee18069fdd264027e7da22165"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9038442d353f8b8dc15786f1efaad62d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdtps__v3__0.html#ga9038442d353f8b8dc15786f1efaad62d">XWDTPS_ZMR_RSTLN_SHIFT</a>&#160;&#160;&#160;4U</td></tr>
<tr class="memdesc:ga9038442d353f8b8dc15786f1efaad62d"><td class="mdescLeft">&#160;</td><td class="mdescRight">shift for reset pulse  <a href="group__wdtps__v3__0.html#ga9038442d353f8b8dc15786f1efaad62d">More...</a><br /></td></tr>
<tr class="separator:ga9038442d353f8b8dc15786f1efaad62d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga23875fd789deb201c12053d6339c4d43"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdtps__v3__0.html#ga23875fd789deb201c12053d6339c4d43">XWDTPS_ZMR_IRQLN_MASK</a>&#160;&#160;&#160;0x00000180U</td></tr>
<tr class="memdesc:ga23875fd789deb201c12053d6339c4d43"><td class="mdescLeft">&#160;</td><td class="mdescRight">set length of interrupt pulse  <a href="group__wdtps__v3__0.html#ga23875fd789deb201c12053d6339c4d43">More...</a><br /></td></tr>
<tr class="separator:ga23875fd789deb201c12053d6339c4d43"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae16f80502d0c7542dcc7269c62f93701"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdtps__v3__0.html#gae16f80502d0c7542dcc7269c62f93701">XWDTPS_ZMR_IRQLN_SHIFT</a>&#160;&#160;&#160;7U</td></tr>
<tr class="memdesc:gae16f80502d0c7542dcc7269c62f93701"><td class="mdescLeft">&#160;</td><td class="mdescRight">shift for interrupt pulse  <a href="group__wdtps__v3__0.html#gae16f80502d0c7542dcc7269c62f93701">More...</a><br /></td></tr>
<tr class="separator:gae16f80502d0c7542dcc7269c62f93701"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga90391e03ac8d6d1e404a8f654129abbf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdtps__v3__0.html#ga90391e03ac8d6d1e404a8f654129abbf">XWDTPS_ZMR_ZKEY_MASK</a>&#160;&#160;&#160;0x00FFF000U</td></tr>
<tr class="memdesc:ga90391e03ac8d6d1e404a8f654129abbf"><td class="mdescLeft">&#160;</td><td class="mdescRight">mask for writing access key  <a href="group__wdtps__v3__0.html#ga90391e03ac8d6d1e404a8f654129abbf">More...</a><br /></td></tr>
<tr class="separator:ga90391e03ac8d6d1e404a8f654129abbf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1d77314aa941add791ce8d0bfa9ec3b9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdtps__v3__0.html#ga1d77314aa941add791ce8d0bfa9ec3b9">XWDTPS_ZMR_ZKEY_VAL</a>&#160;&#160;&#160;0x00ABC000U</td></tr>
<tr class="memdesc:ga1d77314aa941add791ce8d0bfa9ec3b9"><td class="mdescLeft">&#160;</td><td class="mdescRight">access key, 0xABC &lt;&lt; 12  <a href="group__wdtps__v3__0.html#ga1d77314aa941add791ce8d0bfa9ec3b9">More...</a><br /></td></tr>
<tr class="separator:ga1d77314aa941add791ce8d0bfa9ec3b9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Counter Control register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register controls how fast the timer runs and the reset value and also contains the access code (0x248) to allow writes to the register </p>
</div></td></tr>
<tr class="memitem:ga57d4d9381e95475f46b366139f39ce51"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdtps__v3__0.html#ga57d4d9381e95475f46b366139f39ce51">XWDTPS_CCR_CLKSEL_MASK</a>&#160;&#160;&#160;0x00000003U</td></tr>
<tr class="memdesc:ga57d4d9381e95475f46b366139f39ce51"><td class="mdescLeft">&#160;</td><td class="mdescRight">counter clock prescale  <a href="group__wdtps__v3__0.html#ga57d4d9381e95475f46b366139f39ce51">More...</a><br /></td></tr>
<tr class="separator:ga57d4d9381e95475f46b366139f39ce51"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8459363e0e0ad2d44291c68dfaa444d0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdtps__v3__0.html#ga8459363e0e0ad2d44291c68dfaa444d0">XWDTPS_CCR_CRV_MASK</a>&#160;&#160;&#160;0x00003FFCU</td></tr>
<tr class="memdesc:ga8459363e0e0ad2d44291c68dfaa444d0"><td class="mdescLeft">&#160;</td><td class="mdescRight">counter reset value  <a href="group__wdtps__v3__0.html#ga8459363e0e0ad2d44291c68dfaa444d0">More...</a><br /></td></tr>
<tr class="separator:ga8459363e0e0ad2d44291c68dfaa444d0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadd87253d3c5419b22ea299760058ab00"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdtps__v3__0.html#gadd87253d3c5419b22ea299760058ab00">XWDTPS_CCR_CRV_SHIFT</a>&#160;&#160;&#160;2U</td></tr>
<tr class="memdesc:gadd87253d3c5419b22ea299760058ab00"><td class="mdescLeft">&#160;</td><td class="mdescRight">shift for writing value  <a href="group__wdtps__v3__0.html#gadd87253d3c5419b22ea299760058ab00">More...</a><br /></td></tr>
<tr class="separator:gadd87253d3c5419b22ea299760058ab00"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf030acbc21b20d7cb8a857a10cb965ed"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdtps__v3__0.html#gaf030acbc21b20d7cb8a857a10cb965ed">XWDTPS_CCR_CKEY_MASK</a>&#160;&#160;&#160;0x03FFC000U</td></tr>
<tr class="memdesc:gaf030acbc21b20d7cb8a857a10cb965ed"><td class="mdescLeft">&#160;</td><td class="mdescRight">mask for writing access key  <a href="group__wdtps__v3__0.html#gaf030acbc21b20d7cb8a857a10cb965ed">More...</a><br /></td></tr>
<tr class="separator:gaf030acbc21b20d7cb8a857a10cb965ed"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga25fcda0719e4ead71bd6bef791c7ec83"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdtps__v3__0.html#ga25fcda0719e4ead71bd6bef791c7ec83">XWDTPS_CCR_CKEY_VAL</a>&#160;&#160;&#160;0x00920000U</td></tr>
<tr class="memdesc:ga25fcda0719e4ead71bd6bef791c7ec83"><td class="mdescLeft">&#160;</td><td class="mdescRight">access key, 0x248 &lt;&lt; 14  <a href="group__wdtps__v3__0.html#ga25fcda0719e4ead71bd6bef791c7ec83">More...</a><br /></td></tr>
<tr class="separator:ga25fcda0719e4ead71bd6bef791c7ec83"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9c5980e1118cff3e565fcc1f3b6e140a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdtps__v3__0.html#ga9c5980e1118cff3e565fcc1f3b6e140a">XWDTPS_CCR_PSCALE_0008</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memdesc:ga9c5980e1118cff3e565fcc1f3b6e140a"><td class="mdescLeft">&#160;</td><td class="mdescRight">divide clock by 8  <a href="group__wdtps__v3__0.html#ga9c5980e1118cff3e565fcc1f3b6e140a">More...</a><br /></td></tr>
<tr class="separator:ga9c5980e1118cff3e565fcc1f3b6e140a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga77aab579ac71f7ac44d785ff35564c05"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdtps__v3__0.html#ga77aab579ac71f7ac44d785ff35564c05">XWDTPS_CCR_PSCALE_0064</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga77aab579ac71f7ac44d785ff35564c05"><td class="mdescLeft">&#160;</td><td class="mdescRight">divide clock by 64  <a href="group__wdtps__v3__0.html#ga77aab579ac71f7ac44d785ff35564c05">More...</a><br /></td></tr>
<tr class="separator:ga77aab579ac71f7ac44d785ff35564c05"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5a1088e125265e83d8f75a4e39110ee6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdtps__v3__0.html#ga5a1088e125265e83d8f75a4e39110ee6">XWDTPS_CCR_PSCALE_0512</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:ga5a1088e125265e83d8f75a4e39110ee6"><td class="mdescLeft">&#160;</td><td class="mdescRight">divide clock by 512  <a href="group__wdtps__v3__0.html#ga5a1088e125265e83d8f75a4e39110ee6">More...</a><br /></td></tr>
<tr class="separator:ga5a1088e125265e83d8f75a4e39110ee6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac45a97f7c45ce5c10365a27c199d8d2c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdtps__v3__0.html#gac45a97f7c45ce5c10365a27c199d8d2c">XWDTPS_CCR_PSCALE_4096</a>&#160;&#160;&#160;0x00000003U</td></tr>
<tr class="memdesc:gac45a97f7c45ce5c10365a27c199d8d2c"><td class="mdescLeft">&#160;</td><td class="mdescRight">divide clock by 4096  <a href="group__wdtps__v3__0.html#gac45a97f7c45ce5c10365a27c199d8d2c">More...</a><br /></td></tr>
<tr class="separator:gac45a97f7c45ce5c10365a27c199d8d2c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Restart register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register resets the timer preventing a timeout.</p>
<p>Value is specific 0x1999 </p>
</div></td></tr>
<tr class="memitem:ga798fcec0eac576d8309e3995e3597b3e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdtps__v3__0.html#ga798fcec0eac576d8309e3995e3597b3e">XWDTPS_RESTART_KEY_VAL</a>&#160;&#160;&#160;0x00001999U</td></tr>
<tr class="memdesc:ga798fcec0eac576d8309e3995e3597b3e"><td class="mdescLeft">&#160;</td><td class="mdescRight">valid key  <a href="group__wdtps__v3__0.html#ga798fcec0eac576d8309e3995e3597b3e">More...</a><br /></td></tr>
<tr class="separator:ga798fcec0eac576d8309e3995e3597b3e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Status register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register indicates timer reached zero count. </p>
</div></td></tr>
<tr class="memitem:ga79c7165641f0f9b4e356675fc0d0960b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdtps__v3__0.html#ga79c7165641f0f9b4e356675fc0d0960b">XWDTPS_SR_WDZ_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga79c7165641f0f9b4e356675fc0d0960b"><td class="mdescLeft">&#160;</td><td class="mdescRight">time out occurred  <a href="group__wdtps__v3__0.html#ga79c7165641f0f9b4e356675fc0d0960b">More...</a><br /></td></tr>
<tr class="separator:ga79c7165641f0f9b4e356675fc0d0960b"><td class="memSeparator" colspan="2">&#160;</td></tr>
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